Talks to Watch

C++ and Beyond 2012: Herb Sutter - atomic Weapons 2 of 2

29K views · Nov 6, 2017 · 1:32:33 · 2 HN recommenders · 6 mentions · discussed 2019–2024

Part two of Herb Sutter's C++ and Beyond 2012 session on atomic weapons, a deep dive into the C++ memory model, atomics, memory ordering, and hardware behavior. It ends with the modern meaning of volatile.

Why Hacker News points people here: HN recommends it as an in-depth, practical introduction to atomics and weak versus strong memory ordering, relevant to ARM and Rust as well as C++.

“For a more in depth introduction to the topic with a lot of practical code examples, I highly recommend”HN comment, 2023

What Hacker News said 6

Strongly recommendsNobodyNadaNov 2023

“For a more in depth introduction to the topic with a lot of practical code examples, I highly recommend”

In-depth introduction with practical code examples

Full comment

For a more in depth introduction to the topic with a lot of practical code examples, I highly recommend Herb Sutter’s excellent talk: Part 1 link Part 2 this video

in “C++ Memory Model: Migrating from x86 to ARM” · view on HN
Strongly recommendschc4Aug 2024

“which are extremely good”

Top recommendation for learning atomics and concurrency

Full comment

"Is Parallel Programming Hard, And, If So, What Can You Do About It?" is one of the best books about atomics and concurrency, and my #2 recommendation. link My #1 actually isn't a book at all, but the two "atomic Weapons" talks by Herb Sutter, which are extremely good. link this video

in “Rust Atomics and Locks (2023)” · view on HN
Cites itoconnor663May 2019

“goes over the modern meaning of volatile towards the end”

Modern meaning of volatile, covered near the end

Full comment

Herb Sutter's (three hour long!) Atomic Weapons talk goes over the modern meaning of volatile towards the end: this video

in “Ways to break your systems code using volatile (2010)” · view on HN
Cites itNobodyNadaOct 2021

“atomic instructions with relaxed or acquire/release semantics”

More detailed discussion of weak vs strong memory ordering

Full comment

It’s true that ARM alone isn’t the reason for the M1’s performance, but it’s definitely a significant factor. x86 is old — modern x86 chips are still backwards-compatible with the original 8086 from 1978 — and it’s stuck with plenty of design decisions that might have been the correct choice sometime within the past 45 years but no longer today. Whereas the M1 only implements AArch64, a complete redesign of the ARM architecture from 2012, so it doesn’t have to deal with legacy architectural baggage. (We’ve known x86 was the wrong design since the 80’s — hence why there’s no Intel chips in smartphones — but it hasn’t been realistic for anybody except Apple to spend 10 years and billions of dollars to make a high-performance non-x86 chip.) Some examples: - x86 guarantees strong memory ordering on multi-processor systems, which adds completely unnecessary overhead to every memory access. arm64 uses a weak memory model instead, providing atomic instructions with relaxed or acquire/release semantics (see this video for a more detailed discussion). This significantly improves performance all around the board, but especially with reference counting operations (which are extremely common and often a bottleneck in code written in ObjC/Swift): link > fun fact: retaining and releasing an NSObject takes ~30 nanoseconds on current gen Intel, and ~6.5 nanoseconds on an M1 - x86 instruction decode is pretty awful, a significant bottleneck, and not parallelizable due to the haphazardly-design

in “Ask HN: What does one look for in a laptop these days?” · view on HN
Cites itcowtoolsJul 2022

“complicated stuff like memory synchronization”

Memory synchronization complexity

Full comment

I would imagine that any implementation of x86 would have to bear the weight of reverse-compatibility. With reverse comparability, the bad design decisions just compound, for example complicated stuff like memory synchronization this video

in “Ask HN: Can competitors catch up to Apple Silicon?” · view on HN
Cites itmlindnerJan 2023

“he says that ARMv8 Acquire/Release/AcqRel operations are cheaper than SeqCst”

Sutter says ARMv8 acquire/release is cheaper than SeqCst

Full comment

The book, especially chapter 7 seems to say several things completely opposite to what Herb Sutter did in his famous talk a number of years ago. In the book: > This means that on ARM64, sequentially consistent operations are exactly as cheap as acquire and release operations. Or, rather, that ARM64 Acquire, Release, and AcqRel operations are as expensive as SeqCst. Unlike x86-64, however, Relaxed operations are relatively cheap, as they don’t result in stronger ordering guarantees than necessary. However in Herb Sutter's talk (specifically the second half here: this video ) he says that ARMv8 Acquire/Release/AcqRel operations are cheaper than SeqCst. This book seems to claim that x64 is somehow superior to ARMv8, which from my understanding is completely wrong.

in “Rust Atomics and Locks: Low-Level Concurrency in Practice” · view on HN