7K views · Jul 13, 2017 · 35:45 · 3 HN recommenders · 3 mentions · discussed 2017–2018
Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.
Why Hacker News points people here: HN points to it as a technical talk from a chip designer on why AI hardware should put memory close to compute and use async data transfers.
“Here's a nice technical talk from Graphcore's CTO about that”HN comment, 2017
“Moving computation close in with memory, and making data transfers async will speed up DL.”
Graphcore's approach of memory near compute and async transfers.
Interesting approach, but very far off. I prefer GraphCore as a promising new lead in AI hardware. Moving computation close in with memory, and making data transfers async will speed up DL. this video
“Here's a nice technical talk from Graphcore's CTO about that”
Technical talk from Graphcore's CTO on new AI chips.
Indeed, and that's why there are a couple of startups working on new chips and why Google has the TPU. Here's a nice technical talk from Graphcore's CTO about that this video
“isn't quite the presentation I saw, but it has quite a lot of overlap.”
Overlaps heavily with a talk on Graphcore's tile architecture and power.
I went to a talk from the CTO of Graphcore ( link ) on Monday. They are designing chips targeted at machine learning. As I understood it, their architecture comprises - lots of "tiles" - small processing cores with collocated memory (essentially DSPs) - very high bandwidth (90TB/s!) switching fabric to move data between tiles - "Bulk Synchronous Parallel" operation, meaning that the tiles do their work and then the switching fabric moves the data, and then we repeat. The key challenge he pointed to was power - both in terms of getting energy in (modern CPUs/GPUs take similar current to your car starter motor!) and also getting the heat out. Logic gates take a lot more power than RAM, so he argued that collocating small chunks of RAM right next to your processing core was much better from a power perspective (meaning you could then pack yet more into your chip) as well as obviously being better from a performance perspective. this video isn't quite the presentation I saw, but it has quite a lot of overlap. Hope that helps!
